I. Field
The present invention relates generally to communication systems, and more particularly to serializer/deserializer (SerDes) circuits used in communication systems.
II. Background
SerDes circuits are generally incorporated into integrated circuits and operate at high speed, and convert parallel data to serial data and serial data to parallel data.
Conventional SerDes have the following disadvantages:—they use First In-First Out (FIFO) circuits to cross clock domains, thereby requiring extra power and area—they use high speed mux's to manage the bit selection for the output path which adds asymmetry to the waveform or adds an additional pipeline flip flop of latency.